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Review Paper on Reduced Power Consumption using Flip Flop

Skanda H. G., K. B. Ramesh

Abstract


Here we are going to discuss the power utilisation and area minimization using flip flops. The flip flop in the given circuit has two stable states and can be used to store information. The circuit can be made to change state by signals applied to one input and will have one or more output. As, the biggest problem in the Industry is to reduce power utilisation and area reduction. So we have introduced the brief idea of using multi bit flip flop (using D flip flop) and dynamic D flip flop.

 

Keywords: Trigger, pulse clock, FFs length of wire power, multi bit flip flop

 


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References


Kumari, D. P., Rao, R. S. P., & Bhaskar, B. V. (2012). A future technology for enhanced operation in flip-flop oriented circuits. Int J Eng Res Appl, 2(4), 2177-2180.

Alie, S. G., Chandel, T. A., & Dar, J. R. (2014). Power and delay optimized edge triggered D flip-flops for low power microcontroller. Int. J. Sci. Res. Publ, 4(5).

Stojanovic, V., & Oklobdzija, V. G. (1999). Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE Journal of solid-state circuits, 34(4), 536-548.

Aswal, D., Butala, M., Singh, N. A research paper on flip flops. IJIRT, 1(12).


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