

Ensemble Learning for Wafer Classification with Minimum Pre-Labelled Data
Abstract
Data quality during training is crucial for building accurate and reliable machine learning and deep learning models. Obtaining annotations relies heavily on the expertise of domain professionals. Prioritizing manual data labelling is crucial for capturing expert knowledge in machine learning, despite its laborious and time-intensive nature in supervised learning. However, Manual annotation is susceptible to distractions, leading to errors and mislabelling and posing significant disadvantages for data labelling processes in supervised learning. This paper elaborates on the pattern recognition of wafer defect map and the ultimate goal of the paper is to train the convolutional neural network. This deep learning model exhibits confidence in its predictions while requiring minimal pre-labelled data for accurately classifying wafer patterns. It is also capable of pseudo-labelling the wafer maps. For this process, deep model is used to perform the proposed method which involves a series of CNN layers. The paper presents hybrid ensembling as a distinctive method to improve wafer classification efficiency. This approach aims to minimize the need for manual annotation compared to existing methodologies.
References
N. Yu, Q. Xu, and H. Wang, “Wafer defect pattern recognition and analysis based on convolutional neural network,” IEEE Trans. Semicond. Manuf., vol. 32, no. 4, pp. 566–573, Nov. 2019.
J. Yu, “Enhanced stacked denoising autoencoder-based feature learning for recognition of wafer map defects,” IEEE Trans. Semicond. Manuf., vol. 32, no. 4, pp. 613–624, Nov. 2019.
T.-H. Tsai and Y.-C. Lee, “A light-weight neural network for wafer map classification based on data augmentation,” IEEE Trans. Semicond. Manuf., vol. 33, no. 4, pp. 663–672, Nov. 2020.
M. Saqlain, Q. Abbas, and J. Y. Lee, “A deep convolutional neural network for wafer defect identification on an imbalanced dataset in semiconductor manufacturing processes,” IEEE Trans. Semicond. Manuf., vol. 33, no. 3, pp. 436–444, Aug. 2020.
H. S. Shon, E. Batbaatar, W.-S. Cho, and S. G. Choi, “Unsupervised pre-training of imbalanced data for identification of wafer map defect patterns,” IEEE Access, vol. 9, pp. 52352–52363, 2021.
T. Yuan, W. Kuo, and S. J. Bae, “Detection of spatial defect patterns generated in semiconductor fabrication processes,” IEEE Trans. Semicond. Manuf., vol. 24, no. 3, pp. 392–403, Aug. 2011.
Y. Kong and D. Ni, “A semi-supervised and incremental modeling framework for wafer map classification,” IEEE Trans. Semicond. Manuf., vol. 33, no. 1, pp. 62–71, Feb. 2020.
M.-J. Wu, J.-S. R. Jang, and J.-L. Chen, “Wafer map failure pattern recognition and similarity ranking for large-scale data sets,” IEEE Trans. Semicond. Manuf., vol. 28, no. 1, pp. 1–12, Feb. 2015. [9] G. Tello, O. Y. Al-Jarrah, P. D. Yoo, Y. Al-Hammadi, S. Muhaidat, and U. Lee, “Deep-structured machine learning model for the recognition of mixed-defect patterns in semiconductor fabrication processes,” IEEE Trans. Semicond. Manuf., vol. 31, no. 2, pp. 315–322, May 2018.
K. Kyeong and H. Kim, “Classification of mixed-type defect patterns in wafer bin maps using convolutional neural networks,” IEEE Trans. Semicond. Manuf., vol. 31, no. 3, pp. 395–402, Aug. 2018.
J. Wang, Z. Yang, J. Zhang, Q. Zhang, and W.-T. K. Chien, “AdaBalGAN: An improved generative adversarial network with imbalanced learning for wafer defective pattern recognition,” IEEE Trans. Semicond. Manuf., vol. 32, no. 3, pp. 310–319, Aug. 2019.
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