Simulation and Synthesis of Arp Packet Transmission and Reception on FPGA

Abstract

This project is designed in order to understand the implementation of ARP (Address Resolution Protocol). Initially we create an ARP packet in the NIOS software in embedded C language which is present on the FPGA (Field Programmable Gate Array) itself. Code cannot be directly dumped on the physical Layer; hence we write a VHDL code in the QUARTUS II software which will basically receive the NIOS code. Once the ARP packet is received by the QUARTUS II software it sends that packet to the physical. Later, with the help of an 8 bit Ethernet cable we can send the ARP request to the PC. Once the ARP packets are received by the PC, it then sends it back to the physical, which is then transferred on the FPGA and then finally to the NIOS software. The software checks whether it’s an ARP packet or not, if yes, then it checks the destination IP address if that matches then an ARP reply is sent. This reply will consist of the MAC address of the PC which can be deduced by using software called as WIRESHARK.

Keywords: ARP, MAC, FPGA, IP address