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Improvement of a Johnson Counter

Ramesh Kushwaha

Abstract


Johnson counters are notable and broadly utilized in different computerized frameworks, for example, shift registers, recurrence dividers, succession generators and so on. Anyway their execution can be intricate and wasteful, prompting higher power utilization and bigger circuit size. Inside this paper, we propose a rearranged and effective engineering of the Johnson counter which is a superior rendition of a low power plan of a 4-cycle Johnson Counter that is planned by the Clock empower technique utilizing rationale doors and flip-flops. This plan diminishes the power utilization, subsequently diminishing the circuit size and making it more proficient. Moreover, this plan displays quicker engendering delays, empowering quicker information move. The proposed plan is approved through re-enactment and contrasted it and existing plans, showing huge enhancements with regards to effortlessness, proficiency and execution.


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References


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