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Design of MUX Based Circuit For Half Adder And Half Subtractor

Kiran Deshapande, K. B. Ramesh

Abstract


This study delves into crafting a circuit that seamlessly performs both half addition and half subtraction. Leveraging two 2:1 Multiplexers, an XOR gate, and NOT gates, the design achieves dual functionalities while optimizing component usage. A control signal dictates the operational mode, ensuring adaptability with a straightforward assembly of common components. While this integrated circuit offers a compact and versatile solution for fundamental arithmetic operations, it's primarily suited for single-bit tasks and necessitates an extra control signal.

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References


Digital logic and computer design by M. MORRIS MANO twenty second impression.2024.

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Design of energy efficient static level restorer based half subtractor using CNFETs.2022.

Design of three valued logic half subtractor using GNRFET.2022.

2:1 MUX design using multitudinous logic families at 45nm technology.2021.

Design and implementation of high speed hybrid carry select adder.2021.


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