Analysing the Mutliplier Circuit Based on Various Parameters

Abstract

A multiplier circuit used in digital electronics is basically to multiply two or more numbers. Multipliers in Arithmetic logic unit of a computer are used to multiply both signed and unsigned numbers. The three most important design specifications that are to be considered during the manufacturing process are delay, area and power consumption. Delay in the multiplier is directly proportional to the delay in the circuit. Therefore, research is going on in the electronics industry on how to reduce the delay of the circuit by reducing the delay of the multipliers in it. The main purpose of the research is to increase the speed and lower the power consumption even after decreasing the silicon area of the circuit. The fact is that area and speed are two contradictory parameters in an electronic circuit. Hence, by increasing the speed always leads to the use of more and complex hardware. The focus of this paper is to review the multiplier circuits implemented based on various algorithms and compare them based on time delay and area.

Keywords: Multiplier, adder, time delay, area, booth’s algorithm, wallace algorithm, vedic multiplication