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A MOD 13 binary Down Counter's Design and Construction

Raj Singh

Abstract


This paper explains how to use 180 nm CMOS technology transistors to create and synthesize a MOD 13 binary down counter. There are numerous applications for counters. Some start counting from zero and change the output's state when it reaches a predetermined value, while others start counting from zero and change the output's state when it reaches the predetermined value. The counter module is the most important parameter of the counter because it controls how many pulses the counter can count at once. In order to provide an output that activates when the zero count or another pre-set value is reached, it is occasionally done to tally "down" from a predetermined value to zero. This is in addition to tallying up from zero and elevating or incrementing to a predetermined number. The counter then produces a binary number sequence that ranges from 0 to 2n - 1, where n is the counter's bit capacity. A modulo 13 counter needs at least four bits (triggers) and a reset circuit to reset the counter's outputs to zero when the maximum value (13) is reached. The count begins and ends with the combination 11102.Transient simulations of circuits are carried out. The integrated circuit layout is finished after an analysis to make sure the circuit works properly. Physically associating the parts brought about a completed item. The layout is tested to see how it works at the end.Because the output signals are affected by parasitic resistances and capacitances, it is used to determine the maximum clock frequency that can be used (FCLK).

Keywords: Digital counters, binary counters, flip-flops, electronic counter, MOD 13 counter

 


 


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References


Seireg, R. H., Barbour, A. E., & Vacroux, A. G. (1989, August). A general approach to the design of modulo N asynchronous counters with 50% duty cycle. In Proceedings of the 32nd Midwest Symposium on Circuits and Systems, (pp. 685-688). IEEE.

Katreepalli, R., & Haniotakis, T. (2017, April). Energy-efficient synchronous counter design with minimum hardware overhead. In 2017 International Conference on Communication and Signal Processing (ICCSP) (pp. 1423-1427). IEEE.

Baker, R. J. (2019). CMOS: circuit design, layout, and simulation. John Wiley & Sons.

Sarkar, S. K., De, A. K., & Sarkar, S. (2014). Foundation of digital electronics and logic design. CRC Press.

Natarajan, D. (2020). Fundamentals of Digital Electronics. Springer International Publishing.


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