Open Access
Subscription Access
Strategy and Study of Low Power Full Adder Using CMOS
Abstract
In this paper, our thing is to design a completely integrated low power adder with a small number of transistors and to assay calculated values similar as Power, Delay and Product Delay Power (PDP) using 45 nm CMOS process technology. The adder cell is compared to a many generally used adversary types with different configuration of transistors. The full cell of the proposed adder has low power consumption, original effectiveness. Completely designed add- ons were tested by modeling the reverse of the structure with a 45 nm CMOS technology using the Cadence tool.
Keywords: Double pass transistor (DPL) adder, carry lookahead (CLA) adder, domino CMOS logic, DPL multiplier, CLA multiplier
References
Sauer, C., Stanacevic, M., Cauwenberghs, G., & Thakor, N. (2005). Power harvesting and telemetry in CMOS for implanted devices. IEEE Transactions on Circuits and Systems I: Regular Papers, 52(12), 2605-2613.
Ramkumar, B., & Kittur, H. M. (2011). Low-power and area-efficient carry select adder. IEEE transactions on very large scale integration (VLSI) systems, 20(2), 371-375.
Navi, K., Foroutan, V., Azghadi, M. R., Maeen, M., Ebrahimpour, M., Kaveh, M., & Kavehei, O. (2009). A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter. Microelectronics Journal, 40(10), 1441-1448.
Vollmer, H., Schnoor, H., Reith, S., Galota, M., & Creignou, N. (2012). Complexity classifications for different equivalence and audit problems for Boolean circuits. Logical Methods in Computer Science, 8.
Franklin, A. B., & Sasilatha, T. (2019). Design and Analysis of Low Power Full Adder for Portable and Wearable Applications. International Journal of Recent Technology and Engineering (IJRTE) ISSN, 2277-3878.
Refbacks
- There are currently no refbacks.