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Built-in Self-Test Algorithm for Functional Broadside Tests

Kiran Kumar Gopathoti, G. Sunil Kumar

Abstract


In this paper, we propose a technique for weighted test sequence generation for synchronous sequential circuit’s on-chip. Three weights—0, 0.5, and 1—are adequate for combinational circuits to completely cover stuck-at failures because they can accurately duplicate any given test pattern. We define the weights for sequential circuits based on subsequences of a deterministic test sequence. These weights enable us to partially replicate the test sequence and assure that the resulting weighted test sequences would receive full fault coverage. This accumulator-based 3-weight test pattern generating system is demonstrated and more effectively addresses the fundamental shortcomings of the suggested scheme. Compared to traditional techniques of creating test sequences for complicated large-scale systems, the weighted random test pattern generation represents a major improvement.


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References


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