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Fault Diagnosis using Low Density Parity Check

V. Raghavendran, P. Muthukumar, R. Raja Mani

Abstract


The reliability of the instrument was measured using various error analyses. FPGA-based hardware can be application-specific and application-dependent. In this paper we propose a breakdown analysis based on LDPC (Low Density Parity Analysis). The C432 signaling circuit was programmed using the LDPC method to check for circuit faults. By continuously changing the register bits, the circuit is checked for errors. The performance of the signal circuit shows the efficiency of fault diagnosis based on the LDPC approach. A comparative analysis between the BCH (Bose, Chaudhuri, Hocquenghem) and the proposed LDPC confirms the fault tolerance of the FPGA.


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References


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