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DEVELOPMENT AND VALIDATION OF NAND POWER MODEL

Govind Gowda S., Veena M. B.

Abstract


Flash memories are non-volatile memories based on floating-gate transistor that doesn’t require power in order to retain data. NAND Flash is one of the popular solid-state memory storage technologies, where several transistors are series connected and a bit line is pulled low only when all the word lines are at a high state. Most of the electronic gadgets use flash memory for storage and these flash memories are increasingly replacing hard disk drives as the primary storage elements in servers, desktop, and laptop.

In this paper power model is developed for NAND memory and the theoretical values are validated with the test results. The current, voltage and timing parameters are measured across NAND and controller side of Solid State Drive. The power model design is for calculating power dissipated during read, write and erase by NAND memory.

Power model for SDRAM is available with vendors, but as far as NAND is concerned there is no such Power Model readily available for NAND flash memories.


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References


NAND Specification - ONFI Datasheet 2017.

NAND Memory - FortisFlash™ Datasheet, Micron, 2017.

Mario Sako, Yoshihisa Watanabe, Takao Nakajima, “A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology”, IEEE International Conference on Cognitive Computing and Information Processing, 2016.

Tsukasa Kobayashi, Masashi Yamaoka, and Ryuji Yamashita, “A Low Current MLC NAND-Flash Memory in 15 nm CMOS Technology”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016.

Hyunsuk Kim, Su-JinAhn, Yu Gyun Shin, Kyupil Lee, “Evolution of NAND Flash Memory: from 2D to 3D as a storage market leader”, IEEE INTERNATIONAL TEST CONFERENCE, 2017.

Taehyung Kim, Gyuyeol Kong, XiWeiya, and Sooyong Choi, “Cell-to-Cell Interference Compensation Schemes for MLC NAND Flash Memory”, IEEE on Memory Technology, Design, and Testing, 2013.


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