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Analysis of an Efficient Approach to Tolerate Soft Errors in Combinational Circuits

Manuj P., K. B. Ramesh

Abstract


In recent years, soft errors happen in the combinational logic circuits that genuinely impact the action of digital frameworks. Hence, the soft error has ended up a matter of great concern for unwavering quality issues at show. To extend the soft error tolerance, this paper proposes a modern method that will diminish the failure rate of the combinational circuits. A method has been introduced which is able discover out the foremost common minterms of Boolean polynomial math. And these minterms are secured by different cubes to maximize the logical veiling probability, which reduces the failure rate of a combinational circuit. The experimental study appears how the probability of circuit failure is diminished for a given combinational circuit.

 Keywords: Soft errors, combinational circuits, reliability, logical masking, failure probability

 

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References


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