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A Five Input Majority Gate for an Optimal Odd Parity Generator Design in Quantum Dot Cellular Automata
Abstract
An odd equality generator is a device that produces an equality bit that, when added to a double code line, ensures that the string's total number of 1-bits is odd. The odd parity generator concept proposed in this project is new and efficient, utilizing a majority gate and a simple inverter. The QCA 3-bit odd parity generator outperforms the competition in terms of cell count area and delay. Similar to the number of semiconductors in CMOS circuits, QCA circuits have an equivalent number of cells. Reducing the number of cells and QCA wire intersections makes the scheme successful. Reducing the circuit's size and increasing the QCA circuits' activity rate are the main objectives. The suggested 3-bit odd parity generator demonstrates the intended result. Using QCA Fashioner 2.0.3, the plan is reproduced, yielding an effective result.
References
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