Design of Different Interconnect Circuit Techniques for Future Interconnects

Abstract

Chip size shrinks as a result of VLSI's aggressive technology scaling. In a number of ways, this ongoing miniaturization of VLSI devices has a significant impact on the interconnects. Crosstalk, signal delay, and ground noise affect interconnects in high-speed applications, reducing system performance. As a result, circuit performance is becoming limited by interconnects. A comparison of various interconnect circuit techniques for on-chip interconnects is presented in this paper. Using RC and RLC interconnects, we compared various circuit structures. This indicates that the delay benefit for current sensing increases with wire width. Current sensing eliminates any placement constraints and does not necessitate the placement of buffers along the wire, unlike repeaters. The method that required the least amount of energy to implement was differential RLC current mode signaling circuit insertion. Using micro wind in 45nm technology, all of the circuits are simulated and compared to various parameters like power, delay, and energy.