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Design and Implementation of an Optimized ALU using a Square Root Carry Select Adder

Aditya Srinivas, K. B Ramesh

Abstract


Arithmetic logic units (ALUs) are strong combinational circuits in digital computers that carry out arithmetic and logical operations. The Parallel Adder embedded within the Arithmetic Logic Unit (ALU) holds significance, yet the time-consuming nature of carry propagation (CP) during addition demands consideration. To cater to the requirements of low-power and area-efficient applications, the paper suggests an ALU design that integrates a modified Square Root Carry Select Adder (SQRT CSLA). Additionally, for applications necessitating enhanced speed, an alternative ALU design is introduced, incorporating a modified SQRT CSLA. The proposed paper outlines the design and implementation of ALUs with varying bit widths—8-Bit and 16-Bit by adopting the modified SQRT CSLA. This method can also be used on  32-Bit, and 64-Bit.  A comparative analysis has been conducted, contrasting these ALUs with counterparts utilizing a regular SQRT CSLA, specifically focusing on the total number of basic gates. The design process is executed using the Verilog Hardware Description Language (HDL), and simulation is carried out using the ISIM Simulator. The synthesis and implementation phases are performed using Xilinx ISE 12.2, revealing a significant 20.44% reduction in basic gates when employing the ALU featuring the modified SQRT CSLA.


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References


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