Digital Circuit Analysis and Design

Abstract

Stricter societal regulations and the advancement of digital electronic technology have made optimising digital circuit systems a crucial area of study. The ongoing advancement of integrated circuits is accompanied by increasingly serious power consumption problems. The primary design presented in this work is a 4-bit Absolute-Value Detector with A [79.02] FO4(1V), [90.247] Eu(1V). Additionally, we intend to obtain a workable delay power consumption improvement approach by adjusting the device's settings. We have embraced the static CMOS serial adder + comparator circuit style. Furthermore, we examined the non-critical path's and the critical path's power usage and delays. Calculating the voltage, delay, and power usage comes first. Next, we adjust a number of circuit settings, giving up some delay in return for reduced power use. We use it as a trade-off to minimise energy generated on the non-critical way and identify the ratio of the gate sizing in order to calculate the delay of the circuit's main path and determine the optimal percentage of the vdd and sizing to minimise the power consumption, within the specified delay restriction. It can contribute in the desired ways to postpone increment and energy minimisation. We have developed a technique to alter the device's size in the circuit through research. This technique has a certain optimisation effect on the design of digital circuits and can minimise the circuit's power consumption more effectively. Keywords: delay, CMOS circuit, low power consumption.