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An Optimal Design of Odd Parity Generator by Using Five Input Majority Gate in Quantum Dot Cellular Automata
Abstract
Odd equality generator is a gadget that creates an equality bit which when added to a line of double code guarantees that the all-out number of 1-bits in the string is odd. Using a majority gate and a straightforward inverter, this project proposes a novel and efficient odd parity generator design. In terms of cell count area and delay, the QCA 3-bit odd parity generator shines above the competition. The quantity of cells in QCA circuits is like the quantity of semiconductors in CMOS circuits. The plan is made successful by diminishing QCA wire intersections and cell count. The primary goal is to lessen the size of the circuit and to work on the speed of activity of QCA circuits. The desired outcome is demonstrated by the proposed 3-bit odd parity generator. The plan is recreated utilizing QCA Fashioner 2.0.3 which gives effective result.
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