Real-Time Double Fault Tolerant Full Adder Design Using Fault Detection

Abstract

Improved difficulty of the circuit tends to decline the reliability drastically and improved tendency to failure. It is impracticable to form a perfect system so, it is compulsory to make a system fault tolerance. The fault tolerant system is capable of testing specific hardware or software components, power breakdown, or some unpredictable problems and still meet the requirements. In this paper, our aim is to design a low power, area efficient, high speed planned self-checking and self-repairing fault tolerant full adder circuit that can check and restoration multiple faults (single fault and double fault) at the same time and that can spot separate faulty full adder design. The circuit of projected self-checking full adder design is to notice both transient and stable faults as well as it can notice multiple faults at the same instant of time. The proposed design of self-repairing adder repaired multiple faults detected by a self-checking adder. ~100 % detection and correction of fault is reported by the proposed self-checking and self-detecting fault tolerant full adder circuit.