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Design of a Power-Optimized 32-bit RISC-V (RV32I) ALU with Operand Isolation: A Comprehensive Literature Survey

Akash ., Balaji P Garlpet, Basavaraj Idaramani, D Gaurav Rathor, Nataraj Vijapur

Abstract


This paper presents a comprehensive literature survey on low-power Arithmetic Logic Unit (ALU) design techniques for RISC-V processors, covering 28 peer-reviewed works spanning FPGA-based implementations, ASIC physical design flows, power optimization methodologies, and formal verification approaches. A critical research gap is identified: existing techniques predominantly apply clock gating at the register level or architectural optimizations at the system level, failing to eliminate unnecessary switching activity within the combinational ALU functional units. This survey motivates the proposed ActivityAware Operand Isolation technique, which clamps idle unit inputs to zero using a pre-decode gating wrapper, targeting a 30– 35% reduction in Execute-stage dynamic power for the RISC-V RV32I instruction set on 90 nm GPDK using Cadence EDA tools.


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