HW/SW Co-Design Implementation on Zedboard

Abstract

Field Programmable Gate Arrays is an empowering tool for application-oriented methods, provided that a means for rapid prototyping and assessment, as well as algorithm acceleration. Many FPGA dealers have currently started experimenting with embedded processors in their devices, like Xilinx with ARM Cortex A cores, collected with programmable logic cells. These are identified as Programmable System on Chip (PSoC). These ARM cores (embedded in the Processing System or PS) communicate with the programmable logic cells (PL) using ARM standard AXI buses. The hardware setup used in this project is Zedboard along with AD- FMCOMMS2-EBZ is a high speed analog module which has pre- installed IIO OSCILLOSCOPE and GNU RADIO software. The IIO OSCILLSCOPE Linux Application maintains various slots for real time processing and examining the signals attained from the antennas of the analog module. This demand captures the wanted incoming RF signal in the IIO OSCILLOSCOPE where the whole computation is run on to the PS; although the FPGA cloth keeps on idle during this process. During profiling it was found that the most computational expensive block is Fast Fourier transform (FFT) block that took a longer time to display the output. So to lessen the computation time we transfer the FFT block on to the PL side via AXI buses to communicate to the PS side of the board. Due to the parallel nature of FPGA the capability to calculate large mathematical calculation can be made smoother and in lesser time period.

Keywords: Field programmable gate arrays, programmable system on chip, IIO oscilloscope, zed board fast fourier transform, AXI buses