Open Access Open Access  Restricted Access Subscription Access

A Review: Effective Techniques for Hardware Modelling of Machine Learning Algorithms

Amita P. Thakare, Sunil Kumar

Abstract


Machine learning algorithms are complex to model on hardware. This is due to the fact that these algorithms require a lot of complex design systems, which are not easily synthesizable. Therefore, over the years, multiple researchers have developed various state-of-the art techniques, each of them has certain distinct advantages over the others. In this text, we compare the different techniques for hardware modelling of different machine learning (ML) algorithms, and their hardware-level performance. This text will be useful for any researcher or system designer that needs to first evaluate the optimum techniques for ML design, and then inspired by this, they can further extend it and optimize the system’s performance. Our evaluation is based on the 3 primary parameters of hardware design; i.e.; area, energy and delay. Any design technique that can find a balance between these 3 parameters can be termed as optimum. This work also recommends certain improvements for some of the techniques, which can be taken up for further research.

 

Keywords: Hardware, model, machine, learning, optimization

Full Text:

PDF

References


Li, M., Yang, C., Sun, Q., Ma, W. J., Cao, W. L., & Ao, Y. L. (2019). Enabling highly efficient k-means computations on the SW26010 many-core processor of Sunway TaihuLight. Journal of Computer Science and Technology, 34(1), 77-93.

Chauhan, A. S., Sahula, V., & Mandal, A. S. (2019). Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness. Journal of Electronic Testing, 35(5), 581-601.

Gokhale, M., Frigo, J., Mccabe, K., Theiler, J., Wolinski, C., & Lavenier, D. (2003). Experience with a hybrid processor: K-means clustering. The Journal of Supercomputing, 26(2), 131-148.

Mittal, S. (2020). A survey of FPGA-based accelerators for convolutional neural networks. Neural computing and applications, 32(4), 1109-1139.

Tolba, M. F., Saleh, H., Mohammad, B., Al-Qutayri, M., Elwakil, A. S., & Radwan, A. G. (2020). Enhanced FPGA realization of the fractional-order derivative and application to a variable-order chaotic system. Nonlinear Dynamics, 1-12.

Faraone, J., Kumm, M., Hardieck, M., Zipf, P., Liu, X., Boland, D., & Leong, P. H. (2019). Addnet: Deep neural networks using fpga-optimized multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 28(1), 115-128.

Saurav, S., Singh, S., Saini, R., & Saini, A. K. (2016). Hardware accelerator for facial expression classification using linear SVM. In Advances in signal processing and intelligent recognition systems (pp. 39-50). Springer, Cham.

Pietron, M., Wielgosz, M., Zurek, D., Jamro, E., & Wiatr, K. (2013, February). Comparison of GPU and FPGA implementation of SVM algorithm for fast image segmentation. In International Conference on Architecture of Computing Systems (pp. 292-302). Springer, Berlin, Heidelberg.

Majolo, M., & Balbinot, A. (2019). Proposal of a Hardware SVM Implementation for Fast sEMG Classification. In XXVI Brazilian Congress on Biomedical Engineering (pp. 381-386). Springer, Singapore.

Carletti, V., Greco, A., Saggese, A., & Vento, M. (2020). An effective real time gender recognition system for smart cameras. Journal of Ambient Intelligence and Humanized Computing, 11(6), 2407-2419.


Refbacks

  • There are currently no refbacks.