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Triple Gate Spin Field-Effect Transistor Modeling and Applications

P. Kiran Kumar, G. Sunil Kumar, A. Karthik

Abstract


In this research, a mathematical model is used to simulate a Triple Gate Spin-FET with Indium Arsenide in the channel. DC simulations verify the simulation results. Later, different logic functions are achieved by specifying the appropriate channels and several other parameters like spin injection, spin detection, etc. Each gate terminal receives a unique set of inputs. One multi gate spin-FET is used to attain the desired functionality. Using conventional CMOS to achieve the same goals would require a far greater number of chips. The attained capabilities are competitive with designs using VLSI CMOS in terms of power and speed. The table below compares the efficiency of the proposed design to that of the existing VLSI CMOS for the same logic operations.


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References


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