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Shift Register with Low Power and Area Efficient Pulsed Latches

M. Siva Kumar, T.C. Sanjeeva Rayudu

Abstract


A VLSI circuit's fundamental building block is the shift register. Shift registers are frequently employed in a variety of applications, including image processing integrated circuits, digital filters, and communication receivers. The word length of the shifter register has been increased to process huge image data in image processing ICs as the size of the image data continues to expand due to the high demand for high quality picture data. A shift register's architecture is rather straightforward. N data flip-flops are connected in series to form an N-bit shift register. As there is no circuit between flip-flops in the shift register, the size and power consumption are more crucial than flip-flop speed. In this study, pulsed latches are suggested as a low-power and space-efficient shift register. Pulsed latches can be used in place of flip-flops to save space and electricity. By using numerous non-overlaps delayed pulsed clock signals as opposed to the standard single pulsed clock signal, this technique fixes the timing issue between pulsed latches. By arranging the latches into numerous sub shifter registers and utilising additional temporary storage, the shift register only requires a tiny amount of the pulsed clock signals.


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