Open Access Open Access  Restricted Access Subscription Access

Design and Implementation of 4-bit Multiplier using Vedic System

Chirag M, K. B. Ramesh

Abstract


An efficient and fast 4-bit multiplier is designed, analyzed and presented. It is achieved using a Carry-Look Ahead adder, in short CLA adder, circuit. The ancient technique known presently as ‘Vedic Mathematics’ and is based on 'Urdhva Tiryakbhyam sutra' algorithm. This type of modification increases the speed of the asked multiplication by nearly 45%. It further delves into the differences between the traditional method and the proposed method. This article expands further about all the topics mentioned above.


Full Text:

PDF

References


D. M, V. B, S. T and H. K, "Performance Analysis of FPGA Implementation of 4 x 4 Vedic Multiplier using different adder architectures," 2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT), Trichirappalli, India.

A. Patil, S. Kapare, G. Shinde, A. Tekade, M. Andhare and V. Kumbar, "Create a 32-bit Vedic Multiplier and Compare it Against Other Multipliers Using A Carry Look-Ahead Adder," 2023 4th International Conference for Emerging Technology (INCET), Belgaum, India.

J. Suryawanshi, D. Gawade, N. Tank, S. Worlikar and S. Sahu, "Vedic Multiplier Using Carry look ahead adder," 2022 5th International Conference on Advances in Science and Technology (ICAST).

K. Keshav Sai Chowdary, K. Mourya, S. Ravi Teja, et al., “Design of Efficient 16-bit Vedic Multiplier”. International Conference on Signal Processing and Communication.

Vaishali Sharma, R. P. Agarwal, “Design, Implementation & Performance of Vedic Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths,” International Journal for Research in Applied Science & Engineering Technology (IJRASET).

S. Akhter and S. Chaturvedi, "Modified Binary Multiplier Circuit Based on Vedic Mathematics," 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN), Noida, India.

Anuj Sinha, Pramveer and Deshveer, "Design of Vedic multiplier with different adder configurations", IJARSCT.


Refbacks

  • There are currently no refbacks.