DESIGN AND IMPLEMENTATION OF AN POWER EFFICIENT CLOCK PULSED D-FLIP FLOP USING TRANSMISSION GATE

Abstract

In the realm of recent digital applications demanding highly efficient and swift devices with minimal delay and power consumption, this study introduces a low-power clock-pulsed data flip-flop (D flip-flop) featuring a transmission gate. The key innovation lies in the implementation of clock gating to enhance power efficiency. By utilizing an AND gate to interrupt the clock input based on a control signal named Enable, unnecessary transistor switching is curtailed, consequently lowering dynamic power consumption. This clock gating strategy ensures that the clock is deactivated during periods of output stability, reducing power consumption. The performance of the proposed transmission gate-based pulsed D flip-flop is compared between configurations with and without clock gating. The results indicate a power consumption reduction of 1.586 µW in the clock-gated flip-flop compared to its non-gated counterpart. Furthermore, the authors present a 3-bit serial-in and parallel-out shift register employing the proposed D flip-flop, evaluating its performance. The simulations were conducted using the Tanner Electronic Design Automation tool with a 45 nm technology.