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Efficient VHDL Simulation of Convolutional Neural Network Using Parallel Pipelining

Pooja Harish Samudre

Abstract


Artificial Neural Networks are computational devices which are emboldened by the human brain for solving the various computing problems. Currently, Neural Networks are widely applied to resolving problems in different areas such as: image processing, pattern recognition, robotics etc…. Based on the deep learning algorithms, there are many recent rapid growths of applications. A deep learning algorithm which is expanded from Artificial Neural Networks and it is extensively used for picture categorization and identification. The continuing increasing amount of processing required by CNNs creates the field for hardware support methods. Moreover, CNN workloads have a streaming nature, well suited to re-configurable hardware architectures such as FPGAs. Still there is no Neural Network based computing technique, that is parallels pipelining technique has been signified in order to assist the existence of deep neural network in terms of accuracy. In this paper, Computing-based convolutional neural network system produced highly precise and productive system by using parallel pipelining. At the level of neurons, optimizations of the convolutional and fully connected layers are explained and compared. At the network level, approximate computing optimization methods are examined limited by not reducing the accuracy of the network. The proposed convolutional neural network is compared with previous convolutional neural network executed on an FPGA using a computing technique to optimize the time delay and power consumption of the system, with high accuracy as compared to previous conventional neural network implementations.

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References


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