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Enhancing Speed by Optimizing Power and Delay in 4 Bit RALU Utilizing TSG GATE
Abstract
In today's world, the Reversible arithmetic logic unit (RALU) is one of the very important parts of any system with multiple uses in computers, mobile devices, pocket calculators, etc. Reversible logic is useful in mechanical applications of nanotechnology, by eliminating sliding contact, particles in a limited volume can be significantly reduced. Adders and multipliers are the basic building blocks of many computing units. We have implemented a reversible arithmetic logic unit (RALU) based on reversible adders, subtractors, multipliers, and comparators. The reversible adder and subtractor are composed of TSG gates, the reversible multiplier is composed of Fredkin gates and TSGs, and the comparator is based on the BJN gate. For optimization, a reversible 4-bit arithmetic logic block based on 4-bit TSG logic gate is implemented. RALU analyzed by using SIM model and differentiated series analysis in Xilinx 14.1i. Compare the implemented design with maximum combined path delay (MCPD), auxiliary input, garbage output, and delay. The previous algorithm explained the design in a similar way in terms of power consumption and latency. In this proposed algorithm, we focus on power consumption, delay and power consumption factor, so the proposed algorithm is optimizing delay, power consumption and of course power consumption factor.
Keywords: Average power, TSG, delay, RALU and maximum combined path delay
Enhancing Speed by Optimizing Power and Delay in 4 Bit RALU Utilizing TSG GATE
References
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