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Delay and Power Efficient Technique for VLSI Interconnects
Abstract
In this work, Schmitt trigger as an alternate to buffer to reduce delay and power in on-chip interconnects. The most favorable feature of Schmitt trigger is its adjustable threshold voltage; hence the threshold voltage can be chosen or controlled to any level of voltage. Thus a Schmitt trigger can be designed to switch faster than a buffer so that reduction in transition delays. Proposed method is first designed and compared with the buffer. Further, the proposed method is inserted for linear interconnects of various lengths and then on buses which are groups of interconnects. It is shown that the proposed approach is better in terms of delay and power reduction compared to the conventional buffers.
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