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Analysis of Ternary logic arithmetic circuits
Abstract
Complementary metal oxide semiconductor (CMOS) technology has facing a problems when down scaling a device. However, CMOS have the limitations in lower technology, to avoid the drawbacks of CMOS researchers have introduced the carbon nan-tube FETS (CNTFETs). CNTFETs have the flexibility to change the threshold voltage of the device by changing the device dimensions such as length and width. Hence this property of the CNTFET is useful for designing of multi-valued logic (MVL) such as ternary logic. These types of MVL logical circuits are useful for reduction in the hardware of the circuit. Hence, it can be reduce the wiring connection complexity compared to that of other digital logic circuits. This paper presents a CNTFET based ternary arithmetic circuits for the improvement of device complexity because all arithmetic digital circuits are play a major role in many electronic applications. We have verified the functionality of ternary half adder by using CNTFET. All the simulations have done in HSpice using 32nm technology node.
References
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