Open Access Open Access  Restricted Access Subscription Access

The Progressive Journey and Evolution of Power LDMOS Structure: A Review

Sahar Fayaz, Hakim Najeeb -ud-din, G. M. Rather

Abstract


The Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor is a key enabling technology for modern day on-chip power and radio frequency solutions. The conventional LDMOS structure has matured over a span of 5 decades and shown significant improvement in performance. In this review paper, we aim to give a bird’s eye view of the LDMOS technology in terms of the most significant structural developments implemented over its basic structure since it was first reported in the 1970s. This includes techniques like the RESURF, drift region isolation, trench gate structures, stepped gate oxides, dual material gates, sinker, field plates and various doping optimizations.


Full Text:

PDF

References


Y. Tarui, Y. Hayashi, T. Sekigawa, “Diffusion self aligned Enhance-Depletion MOS一IC,” Journal of the Japan Society of Applied Physics, Vol.40, pp.193-198, 1971.

H.J. Sigg, G.D. Vendelin, T.P. Cauge, J. Kocsis, “D-MOS transistor for microwave applications,” IEEE Trans. Electron Devices ED-9(1), 45–53 (1972)

M.J. Deelerq, J.D. Plumfner, “Avalanche breakdown in high voltage DMOS devices,” IEEE Trans. Electron Devices, 23(1): pp. 1-4, 1976

D. Disney and Z. J. Shen, "Review of Silicon Power Semiconductor Technologies for Power Supply on Chip and Power Supply in Package Applications," in IEEE Transactions on Power Electronics, vol. 28, no. 9, pp. 4168-4181, Sept. 2013, doi: 10.1109/TPEL.2013.2242095.

M. Zierak, N. Feilchenfeld, C. Li and T. Letavic, "Fully-isolated silicon RF LDMOS for high-efficiency mobile power conversion and RF amplification," 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's (ISPSD), Hong Kong, China, 2015, pp. 337-340, doi: 10.1109/ISPSD.2015.7123458.

A. Parpia and C. A. T. Salama, “Optimization of RESURF LDMOS transistors: an analytical approach,” IEEE Trans. Electron Devices, vol.37, no. 3, pp. 789-796, Mar 1990

J. A. Appels and H. M. J. Vaes, “High voltage thin layer devices (RESURF devices),” International Electron Devices Meeting, pp. 238-241, 1979.

S. Colak, B. Singer and E. Stupp, "Lateral DMOS Power transistor design," in IEEE Electron Device Letters, vol. 1, no. 4, pp. 51-53, April 1980, doi: 10.1109/EDL.1980.25226

Z. Hossain, M. Imam, J. Fulton and M. Tanaka, "Double-RESURF 700 V n-channel LDMOS with best-in-class on-resistance", Proc. 14th Int. Symp. Power Semiconductor Devices Ics, pp. 137-140, 2002.

D. R. Disney, A. K. Paul, M. Darwish, R. Basecki and V. Rumennik, “A new 800 V lateral MOSFET with dual conduction paths,” Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01, pp. 399-402, Osaka, 2001

M. Qiao et al., "Analytical Modeling for a Novel Triple RESURF LDMOS With N-Top Layer," in IEEE Transactions on Electron Devices, vol. 62, no. 9, pp. 2933-2939, Sept. 2015, doi: 10.1109/TED.2015.2448120.

M. Qiao, Y. Li, Z. Yuan, L. Liang, Z. Li and B. Zhang, "A Novel Ultralow RON,sp Triple RESURF LDMOS With Sandwich n-p-n Layer," in IEEE Transactions on Electron Devices, vol. 67, no. 12, pp.5605-5612, Dec. 2020, doi: 10.1109/TED.2020.3030872.

T. Letavic et al., “High-performance 600V smart power technology on thin layer Silicon-on insulator,” Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs ISPSD’97, p. 49-52, May 1997

J. Sonsky and A. Heringa, “Dielectric Resurf: Breakdown voltage control by STI layout in standard CMOS,” in IEDM Tech. Dig., Dec. 2005, pp. 373–376,doi:10.1109/IEDM.2005.1609354.

R. Ye et al., "Reliability Concerns on LDMOS With Different Split-STI Layout Patterns," in IEEE Transactions on Electron Devices, vol. 67, no. 1, pp. 185-192, Jan. 2020, doi: 10.1109/TED.2019.2951131.

Zhaozhao Xu, Donghua Liu, Jun Hu, Feng Jin, Xinjie Yang, Wenting Duan, Wei Yue, Ziquan Fang, Wensheng Qian, Weiran Kong, Shichang Zou, “Demonstration of improvement of specific on-resistance versus breakdown voltage tradeoff for low-voltage power LDMOS,” Microelectronics Journal, vol. 88, pp. 29-36, 2019, doi: 10.1016/j.mejo.2019.04.011.

D. Ueda, H. Takagi, and G. Kano, “A new vertical power MOSFET structure with extremely reduced on-resistance,” IEEE Trans. Electron Devices, vol. ED-32, no. 1, pp. 2–6, Jan. 1985.

D. Disney, W. Chan, R. Lam, R. Blattner, S. Ma, W. Seng, J.-W. Chen, M. Cornell, R. Williams, “60 V lateral trench MOSFET in 0.35 μm technology,” International Symposium on Power Semiconductor Devices and ICs, Orlando, USA, 2008.

T. Erlbacher, A. J. Bauer and L. Frey, "Reduced On Resistance in LDMOS Devices by Integrating Trench Gates Into Planar Technology," in IEEE Electron Device Letters, vol. 9 31,no.5, pp. 464-466, May 2010, doi: 10.1109/LED.2010.2043049.

Ge Rui et al 2012 J. Semicond. 33 074005, doi: 10.1088/1674-4926/33/7/074005

Yuan Wang, Shengdong Hu, Chang Liu, Jian'an Wang, Han Yang, Shenglong Ran, Jie Jiang, Gang Guo, “Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers”, Results in Physics, Vol 19, 2020, 103589, doi: 10.1016/j.rinp.2020.103589

P.H. Wilson, “A novel trench gate LDMOS for RF applications,” 13th International Crimean Conference on Microwave and Telecommunication Technology, Ukraine, 2003

D. -m. Ke, Q. Liu, J. -n. Chen, S. Gao and L. Liu, "A new dual-material gate LDMOS for RF power amplifiers," 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Shanghai, China, 2006, pp. 242-244, doi: 10.1109/ICSICT.2006.306173

J. -B. Ha, H. -S. Kang, K. -J. Baek and J. -H. Lee, "Enhancement of Device Performance in LDMOSFET by Using Dual-Work-Function-Gate Technique," in IEEE Electron Device Letters, vol. 31, no. 8, pp. 848-850, Aug. 2010, doi: 10.1109/LED.2010.2051134

Ki-Ju Baek, Kee-Yeol Na, Yeong-Seuk Kim,“Electrical characteristics and optimization of extended-drain MOS transistor with dual-workfunction-gate for mixed-signal applications”, Solid-State Electronics, vol. 100, pp. 49-53, 2014, doi: 10.1016/j.sse.2014.07.004

Radhakrishnan Sithanandam and M Jagadesh Kumar, 2010, Semicond. Sci. Technol. 25 015006, doi: 10.1088/0268-1242/25/1/015006

Na, K.Y., Baek, K.J. and Kim, Y.S., “Improvement of the transconductance in a LDMOS transistor with dual gate oxide”, Journal of the Korean Physical Society, 52(4), pp.1128-1132,2008, doi: 10.3938/jkps.52.1128

K.-J. Baek, Y.-S. Kim, and K.-Y. Na, “Performance Optimization of LDMOS Transistor with Dual Gate Oxide for Mixed-Signal Applications,” Transactions on Electrical and Electronic Materials, vol. 16, no. 5, pp. 254–259, Oct. 2015. doi: 10.4313/TEEM.2015.16.5.254

S. -Y. Chen et al., "Study on 20 V LDMOS With Stepped-Gate-Oxide Structure for PMIC Applications: Design, Fabrication, and Characterization," in IEEE Transactions on Electron Devices, vol. 69, no. 2, pp. 878-881, Feb. 2022, doi: 10.1109/TED.2021.3131922.

A. Wood, C. Dragon, W. Burger, “High performance silicon LDMOS technology for 2 GHz RF power amplifier applications,” International Electron Device Meeting, San Francisco, USA,1996

F. van Rijs, “Status and trends of silicon LDMOS base station PA technologies to go beyond 2.5 GHz applications,” IEEE Radio and Wireless Symposium, pp. 69–72, Jan 2008

I. Cortés, J. Roig, D. Flores, J. Urresti, S. Hidalgo, J. Rebollo, “A numerical study of field plate configurations in RF SOI LDMOS transistors”, Solid-State Electron. 50, 155–163, 2006.

Zhang Wenmin et al, “An analytical model for the drain—source breakdown voltage of RF LDMOS power transistors with a Faraday shield”, Journal of Semiconductors, 2012

S. Chahar, G. M. Rather, and N. Hakim, “The effect of shallow trench isolation and sinker on the performance of dual-gate LDMOS device,” IEEE Trans. Electron Devices, vol. 66, no. 1, pp. 585-591, Jan. 2019, doi: 10.1109/TED.2018.2881918

Salih A, Yuan J-S, “Evaluation of LDMOS Figure of Merit Using Device Simulation,” Electronics, 7 no.5:60, 2018, doi: 10.3390/electronics7050060

Bin Yu, C. H. J. Wann, E. D. Nowak, K. Noda and Chenming Hu, "Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET's," in IEEE Transactions on Electron Devices, vol. 44, no. 4, pp. 627-634, April 1997, doi: 10.1109/16.563368.

D. G. Borse et al., "Optimization and realization of sub-100-nm channel length single halo p-MOSFETs," in IEEE Transactions on Electron Devices, vol. 49, no. 6, pp. 1077-1079, June 2002, doi: 10.1109/TED.2002.1003752.

K. Narasimhulu, M. P. Desai, S. G. Narendra and V. R. Rao, "The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance," in IEEE Transactions on Electron Devices, vol. 51, no. 9, pp. 1416-1423, Sept. 2004, doi: 10.1109/TED.2004.833589.

Mohapatra NR, et al., “The impact of channel engineering on the performance and reliability of LDMOS transistors,” Proceedings of 35th European Solid-State Device Research Conference, Grenoble, France, 2005, pp. 481-484, doi: 10.1109/ESSDER.2005.1546689

Kaushal KN, Mohapatra NR, “A Zero Cost Technique to Improve ON-State Performance and Reliability of Power LDMOS Transistors,” IEEE Journal of the Electron Devices Society. vol. 9, pp. 334-341, 2021 doi: 10.1109/JEDS.2021.3059854

Fayaz, S., Hakim, Nud. & Rather, G.M., “Applicability of Channel Doping Gradient in the Design of a Short Channel (0.1 µm) LDMOS Transistor for Integrated Power and RF Applications,” Trans. Electr. Electron. Mater. (2024). https://doi.org/10.1007/s42341-024-00530-7

A. Saadat, M. L. Van De Put, H. Edwards and W. G. Vandenberghe, "Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications," in IEEE Journal of the Electron Devices Society, vol. 8, pp. 711-715, 2020, doi: 10.1109/JEDS.2020.3008388.

Mohit Payal & Yashvir Singh (2017) A Multi-Channel Trench-Gate Radio Frequency LDMOS on Silicon-on-Insulator, IETE Technical Review, 34:3, 246253,doi: 10.1080/02564602.2016.1166993


Refbacks

  • There are currently no refbacks.