

Optimizing TSV Performance in 3D ICs with Perylene-N for Reduced Noise Coupling
Abstract
The continuous demand for smaller and faster electronic devices has driven the semiconductor industry to explore new advancements in integrated circuit (IC) design. Traditional long metal interconnects not only increase the system’s size but also introduce RC delay, which degrades performance by limiting communication bandwidth. To overcome these challenges, 3D IC integration has emerged as a promising solution. This approach involves stacking different functional modules on separate layers of a silicon (Si) substrate, interconnected through Through-Silicon Vias (TSVs). TSVs serve as crucial components that facilitate high-speed electrical connections between layers in 3D structures. However, one of the major challenges in TSV-based 3D ICs is signal degradation due to noise coupling between signal TSVs (aggressors) and ground TSVs (victims). To enhance signal integrity, effective isolation between TSVs and the Si substrate is essential, requiring optimized liner materials and structural designs. Among various dielectric materials, Perylene-N has demonstrated significant potential due to its ability to reduce area and power consumption. This study compares the performance of Perylene-N with conventional SiO₂, Benzocyclobutene (BCB), and Teflon AF 1600 as liner materials for embedded TSVs (ETSVs). The analysis evaluates noise coupling under different conditions, with the proposed dielectric-metal-dielectric arrangement around copper TSVs. Results indicate that Perylene-N provides superior noise isolation compared to conventional SiO₂, achieving a 51 % improvement in noise coupling suppression at THz frequencies, which has been thoroughly validated in this work.
References
Wiley Online Library. (2024). Recent advancements in benzocyclobutene materials for 3D IC integration. Retrieved from https://onlinelibrary.wiley.com/.
ResearchGate. (2024). Development of laser and photo definable toughened benzocyclobutene dielectric materials for 3D-TSV integration. Retrieved from https://www.researchgate.net/.
Journal of Semiconductors. (2009). Wafer-level packaging using BCB interlayer dielectrics. Retrieved from https://www.jos.ac.cn/.
Nanyang Technological University Thesis. (2014). Thermal and fabrication challenges in 3D IC integration using BCB. Retrieved from https://dr.ntu.edu.sg/.
Banerjee, K., Souri, S. J., Kapur, P., & Saraswat, K. C. (2001). 3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proceedings of the IEEE, 89(5), 602-633. https://doi.org/10.1109/5.933469.
Pattanaik, S., et al. (2021). A comprehensive review of 3D IC technology: Challenges and advancements. IEEE Access, 9, 87133-87148. https://doi.org/10.1109/ACCESS.2021.3087879.
Koyanagi, M., et al. (2008). Technology roadmap for 3D IC integration. Advances in Solid State Circuits Technologies. https://doi.org/10.5772/5401.
Souri, S. J., Banerjee, K., Saraswat, K. C. (2000). Multiple Si layer ICs: Motivation, performance analysis, and design implications. Proceedings of the Design Automation Conference (DAC), 213-220.https://doi.org/10.1109/DAC.2000.855288.
Li, Z., & Lim, S. K. (2012). Physical design and reliability analysis for 3D ICs with through-silicon-via (TSV) stacks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 31(2), 188-200. https://doi.org/10.1109/TCAD.2011.2171735.
Tezzaron Semiconductor. (2022). 3D Integrated Circuits. Technical White Paper.http://www.tezzaron.com/.
Refbacks
- There are currently no refbacks.