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Design for Testability (DFT) for a Chip with Memory and Logic

Pradyumna S Acharya, Sujatha D Badiger

Abstract


Faulty chips will reach customer if IC testing is not performed on the fabricated IC. Simple types of testing such as functional and structural testing are not feasible in case of a large circuit. So, Design for Testability (DFT) techniques are needed to be added to the block so that the testing becomes easier and faster. Memory Built in self-test (MBIST) for memory testing and scan insertion for sequential circuits are the major DFT techniques commonly used. DFT insertion is done by using the tool called Tessent shell. After the design is done, patterns are generated by using the tool which target particular fault type. Patterns are generated for stuck at and transition faults detection. After the patterns are generated, the DFT design is verified by simulation using Questasim to check that the expected output is obtained.

 

Keywords: Built in self-test, design for testability, launch off shift, launch off capture, memory testing, scan testing


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References


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