Design and Development of Half Adder Using Various Technologies

Abstract

In this paper, we will be investigating and analysing various techniques for implementing a half adder circuit with the least number of transistors. In digital electronics half adder combinational circuit used to add two numbers. It is a number arithmetic circuit that plays out the arithmetic activity of adding two single-bit words. The half adder procedure, plan of half adder utilizing AVL innovation, plan of a 3-T Half Adder, NMOS pass transistors rationale plan of half adder utilizing 2:1 MUX, half adder circuit plan with CMOS NAND gates, half adder circuit plan with CMOS transmission logic gates in cadence virtuoso. In this part, think about half adder circuit plan procedures and analyse different boundaries of half adder circuit configuration utilized different circuit plan strategies. Customary methods required less number steering assets. A 3-T half-adder circuit performs with less postponement, rapid, little format region, less power utilization and hitter productivity and exactness.

Keywords: CMOS, half-adder, transistors, MUX.