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A Study of Stepped Hetero Channel MOSFET and Hetero Junction Tunnel Fets

Gayatri Mohanta

Abstract


In the current CMOS sub-nano scale regime, hetero channel MOSFETs are one of the capable candidates in high switching speed applications. Out of these group, III-V channel-based MOSFETs become very popular due to their high mobility and high saturation velocity as result it offers high drive with better electrostatic gate control over the channel. A new composite channel layer made of InGaAs/InAs/InGaAs with a metal step gate has been proposed in this work. The formation of a composite layer near the channel enhances the electrostatic control along the channel, as result, there is an improvement in on resistance. The simulation reveals that the performance of the stepped composite (CS) MOSFET is superior to that of the conventional MOSFET. Lower supply voltage reduces MOSFET power consumption. However, the rising off-state leakage current makes it difficult to continue the trend. Sharp subthreshold slope FETs have been studied. Tunneling FET (TFET) minimizes drain bias. High tunnelling resistance limits TFETs' drivability. TFET drivability has been improved by using III-V hetero-junctions. Schottky-suitable silicide/Si construction wall TFETs require defect-free silicide at the boundary and wall controllability. To meet demand, a new silicide-forming method using metal/silicon slim sheet stack annealing is introduced has been demonstrated.


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References


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