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Optimized Single Precision Floating-Point ALU Design and Implementation for RISC Processors on FPGA

SAYYAM JAIN, K. B. Ramesh

Abstract


Single Precision Floating-Point Arithmetic Logic Units (FPALUs) play a crucial role in the performance and functionality of Reduced Instruction Set Computer (RISC) processors. This paper presents the design and implementation of an FPALU tailored for a RISC processor on a Field-Programmable Gate Array (FPGA). The FPALU is optimized for single precision floating-point arithmetic operations, including addition, subtraction, multiplication, and division. The design methodology encompasses the development of essential logic blocks, such as the opcode decoder, arithmetic block, logical block, comparator block, shifter/rotator block, and the specialized floating-point unit (FPU). Each block is meticulously crafted to ensure efficient operation and seamless integration within the RISC processor architecture. The implementation is validated through simulations and experimental analysis, demonstrating the feasibility and effectiveness of the FPALU design on FPGA technology.


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References


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