LOW POWER REDUNDANT TRANSITION FREE-TSPC FLIP FLOPS DOBLE EDGE TRIGGERING BASED ON C ELEMENT AND SINGLE TRANSISTOR CLOCK BUFFER

Abstract

In the modern graphics processing unit (GPU)/artificial intelligence (AI) era, flip-flop (FF) has become one of the most power-hungry blocks in processor When the input signal has been interfered and glitches occur, the power consumption of Double-Edge Triggered Flip-Flops (DETFFs) will significantly increase. To effectively reduce the power consumption, this paper presents an low-power Redundant-Transition- DETFF based on C-elements. And single transistor clocked buffer The STCB uses a single-clocked transistor in the data sampling path, which completely removes clock redundant transitions (RTs) and internal RTs that exist in other DET designs. Verified by post-layout simulations in 22 nm fully depleted silicon on insulator (FD-SOI) CMOS, when operating at 10% switching activity, the proposed STC-DET outperforms prior state-of-the-art low-power DET in power consumption by 14% and 9.5%, at 0.4 and 0.8 V, respectively. It also achieves the lowest power-delay-product (PDP) among the DETs. Index Terms— Dual edge triggering (DET), dynamic power, flip-flop(FF). This DETFF uses an enhanced C-element, which effectively suppresses input signal glitches, avoids redundant transitions within the DETFF, and lowers the transistor's charge and discharge rates. This paper simulates the proposed DETFF using HSPICE. The title, text, headers, and other elements of your paper are already defined in its style sheet by this electronic document, which serves as a "live" template.