Examination of the Mutliplier Circuit Using Different Parameters

Abstract

In digital electronics, a multiplier circuit is essentially used to multiply two or more numbers. Computers utilize multipliers in their arithmetic logic units to multiply both signed and unsigned values. In the production process, the three most crucial design criteria to take into account are power consumption, area, and delay. The multiplier's delay is closely correlated with the circuit's latency. In order to decrease the delay of the circuit by reducing the delay of the multipliers in it, research is being conducted in the electronics sector. The primary goal of the research is to reduce power consumption and boost speed even when the silicon area of the circuit is reduced. The truth is that in an electronic circuit, area and speed are two opposing factors. As a result, accelerating speed invariably necessitates using more sophisticated gear. This work reviews and compares multiplier circuits designed using different techniques in terms of area and time delay.