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Design and FPGA Implementation of a RISC-V Processor Core with Low-Power Enhancements

Samved Mokhashi, Srushti S Patil, Sudiksha S Prakash, Sushmita Sankapal, Sujatha K

Abstract


The rapid expansion of edge computing necessitates microprocessors that are both highly efficient and capable of intelligent decision-making. Traditional pipelined processors waste significant dynamic power during control-flow hazards due to pipeline flushes. This paper presents the design and FPGA implementation of a 32-bit RISC-V (RV32I) 5-stage pipelined processor enhanced with a micro-perceptron branch predictor. By integrating a lightweight artificial neural network directly into the instruction fetch stage, the processor learns branch behaviors to minimize mispredictions, reducing unnecessary pipeline flushes and their associated dynamic power cost. The design was synthesized and implemented on a Basys 3 Artix-7 FPGA board using Vivado. Results indicate a highly optimized footprint utilizing only 4.2% of available Look-Up Tables (LUTs) out of 133,800, while maintaining a 100 MHz clock frequency with a positive timing slack of +7.082 ns. The on-chip power analysis shows a total of 0.143 W with dynamic power of only 13 mW — an estimated 25–40% reduction compared to standard 5-stage RV32I cores at the same frequency — validating the viability of hardware-level AI for low-power embedded systems.


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References


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