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DESIGN OF OPTIMIZED ALU

Spriha Dibbi, K. B. Ramesh

Abstract


The pursuit of enhanced performance  and efficiency in digital circuits has led to a continuous evolution of Arithmetic Logic Units (ALUs) – pivotal components in modern processors. This paper explores novel strategies for optimizing ALU design by dissecting the optimization process into key components. We delve into the intricacies of each design aspect, emphasizing the synthesis of Verilog Hardware Description Language (HDL) for simulation and verification.  The objective is to present a comprehensive view of ALU optimization, addressing both speed and power consumption considerations. Our innovative approach incorporates parallel processing techniques, efficient data path design, and advanced control unit strategies, aiming to redefine the landscape of ALU architectures. Through simulation and analysis, we evaluate the proposed optimizations, demonstrating significant improvements in ALU performance. This paper serves as a valuable resource for researchers and engineers seeking to enhance ALU functionality and efficiency in contemporary processor designs.


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References


A. Yadav, M. Rizkalla, T. Ytterdal, J. J. Lee, L. S. Balasubramanian, and A. Gopinath, "Evaluation of FinFET in Ultra Low Power ALU," in 2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS), 2022.

G. Prasad, "A Tutorial on Design of Datapath and Controller of an ALU using Verilog and Verification using Open Source EDA Tools," in 2021 2nd International Conference on Communication, Computing and Industry 4.0 (C2I4), 2021.

T. Pathade, Y. Agrawal, R. Parekh, and M. G. Kumar, "Effective Low Power ALU Design with Incorporation of MWCNTB On-chip Interconnects," in 2022 IEEE 24th Electronics Packaging Technology Conference (EPTC), 2022.

F. Glaser, S. Mach, A. Rahimi, F. K. Gürkaynak, Q. Huang, and L. Benini, "An 826 MOPS, 210uW/MHz Unum ALU in 65 nm," in 2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018.

N. Gaur, A. Mehra, and P. Kumar, "Enhanced AES Architecture using Extended Set ALU at 28nm FPGA," in 2018 5th International Conference on Signal Processing and Integrated Networks (SPIN), 2018.

Y. P. V, S. Koila, K. K. Muralidharan, and V. Amaresh, "High Performance Field Configurable Data Re-alignment Engine," in 2022 IEEE Women in Technology Conference (WINTECHCON), 2022.

W. S. Osman and S. M. Hashim, "FPGA-Based Pipelined Microprocessor," in 2018 International Conference on Computer, Control, Electrical, and Electronics Engineering (ICCCEEE), 2018.

S. Kundu, G. Datta, P. A. Beerel, and M. Pedram, "qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic Unit," in 2019 IEEE International Superconductive Electronics Conference (ISEC), 2019.

A. Yadav and V. Bendre, "Design and Verification of

bit RISC Processor Using Vedic Mathematics," in 2021 International Conference on Emerging Smart Computing and Informatics (ESCI), 2021.


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