Design and Implementation of Fault Resilience Strategies for Enhanced Digital System Performance

Abstract

This research paper delves into diverse methodologies and insights aimed at optimizing sequential circuits for enhanced performance and reliability in digital systems Safety-critical systems used in applications that require high reliability, performance, and fault tolerance often use sequential logic circuits in their design and implementation. A safety-critical digital system typically uses latches, flip-flops, and other memory elements that are sensitive to the effects of natural failures and radiation-induced single event disturbances (SEU). Defects can cause subsystem failure due to the continuous progress in implementing the small size transistors. To develop a reliable digital system, it is important to develop new fault tolerance techniques that are integrated into the design of the sequential logic circuits. This work proposes a new fault-tolerant approach based on the redundancy of a sequential logic circuit consisting of several -shaped components, D-flip-flops storage elements connected to a fault injection device, two-module aggregation, and data. Switching circuit controls. Finally, we believe that using this new failover and redundancy would improve the reliability and dependability of the next generation safety critical applications.